A typical computer system has at least a microprocessor and memory. The microprocessor processes, i.e., executes, instructions to accomplish various tasks of the computer system. Such instructions, along with the data required by the microprocessor when executing these instructions, are stored in some form of memory. FIG. 1 shows a typical computer system having a microprocessor 10 and some form of memory 12. The microprocessor 10 has, among other components, a central processing unit (also known and referred to as xe2x80x9cCPUxe2x80x9d or xe2x80x9cexecution unitxe2x80x9d) 14 and a memory controller (also known as xe2x80x9cload/store unitxe2x80x9d) 16. The CPU 14 is where the actual arithmetic and logical operations of the computer system take place. To facilitate the execution of operations by the CPU 14, the memory controller 16 provides the CPU 14 with necessary instructions and data from the memory 12. The memory controller 16 also stores information generated by the CPU 14 into the memory 12.
The operations that occur in a computer system, such as the logical operations in the CPU and the transfer of data between the CPU and memory, require power. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation. As an added challenge, power consumption of modem computers has increased as a consequence of increased operating frequencies. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
Often, power generated to a computer system component varies, which, in turn, affects the integrity of the component""s output. Typically, this power variation results from the distance between a power supply for the component and the component itself. This distance may lead to the component not receiving power (via current) at the exact time it is required. One approach used by designers to combat this performance-inhibiting behavior is introducing decoupling capacitance (also referred to as xe2x80x9cdecapxe2x80x9d) to a particular circuit by positioning one or more decoupling capacitors close to the component. These decoupling capacitors store charge from the power supply and distribute the charge to the component when needed. For example, if power received by a component from a power supply attenuates, one or more decoupling capacitors will distribute charge to the component to ensure that the component is not affected by the power variation on the power supply. In essence, a decoupling capacitor acts as a local power supply for one or more specific components in a computer system.
Within a computer system component, such as a circuit, there are two types of decoupling capacitance: implicit and explicit. Explicit decoupling capacitance is provided to the circuit through the use of decoupling capacitors as discussed above. Implicit decoupling capacitance (also known in the art as xe2x80x9cparasitic capacitancexe2x80x9d and also referred to as xe2x80x9cinherent capacitancexe2x80x9d) is capacitance that is inherent in a circuit. Implicit capacitance results from the electromagnetic effects between current-carrying wires. Further, implicit capacitance is a function of the distance between two such wires.
FIG. 2 shows the presence of explicit and implicit decoupling capacitance in a section of a typical computer system component 20. The component 20 has a power supply 22, where power from the power supply 22 is delivered to chip logic 24 via a power supply line 26 and a ground line 28. When there is power variation across the power supply 22, a decoupling capacitor 30 positioned in parallel with the power supply 22 provides charge, i.e., power, to the chip logic 24. In other words, the decoupling capacitor 30 provides explicit decoupling capacitance.
Still referring to FIG. 2, the existence of implicit decoupling capacitances 32, 34 is shown. A first occurrence of implicit decoupling capacitance 32 occurs between the power supply line 26 and a signal path 36 from the chip logic 24. A second occurrence of implicit decoupling capacitance 34 occurs between the signal path 36 and the ground line 28. The implicit decoupling capacitances 32, 34 are dependent on the characteristics of the signal path 36, specifically, whether a signal on the signal path 36 is high or low. When the signal is low, the implicit decoupling capacitance provided to the chip logic 24 is equal to the implicit decoupling capacitance 32 between the power supply line 26 and the signal path 36. Alternatively, when the signal is high, the implicit decoupling capacitance provided to the chip logic 24 is equal to the implicit decoupling capacitance 34 between the signal path 36 and the ground line 28.
In FIG. 2, the first and second occurrences of implicit decoupling capacitance 32, 34 are equal because the distance (shown in FIG. 2 as xe2x80x9cDxe2x80x9d) between the power supply line 26 and signal path 36 and the distance between the signal path 36 and the ground line 28 are equal. Because the signal path 36 is equidistant from the power supply line 26 and the ground line 28, the signal path 36 is said to be xe2x80x9csymmetrically shielded,xe2x80x9d where shielding refers to the providing of capacitance to prevent electromagnetic interference from reaching a signal.
As discussed above with reference to FIG. 2, a signal on the signal path may be high or low, and depending on the value of that signal, the amount of implicit decoupling capacitance present can be determined. In other words, the amount of implicit decoupling capacitance present on a signal path is a function of whether a signal on the signal path is high or low. However, regardless of whether a signal has a tendency to have a particular value, the amount of implicit decoupling capacitance present will be equal to the amount of implicit decoupling capacitance that would be present if the signal had another value. For example, although an AND gate under normal conditions has a tendency to output low, the amount of implicit decoupling capacitance present will be the same for when the AND gate outputs low and when the AND gate outputs high.
According to one aspect of the present invention, a computer system comprises a first wire, a signal path, and at least one other wire, where the first wire is disposed at a first distance from the signal path, where the at least one wire is disposed at a second distance from the signal path, and where the first distance and the second distance are dependent on a probability of a value of a signal on the signal path being at a specific value.
According to another aspect, an integrated circuit comprises a first node, a signal, and at least one other node, where the first node is positioned at a first distance from the signal, where the at least one node is positioned at a second distance from the signal, and where the signal is asymmetrically shielded by the first node and the at least one other node.
According to another aspect, a method for increasing decoupling capacitance in an integrated circuit comprises disposing a first wire at a first distance from a signal, disposing a second wire at a second distance from a signal, and asymmetrically shielding the signal by the first wire and the second wire, where the first distance and second distance are determined by a probability of the signal being at a specific value.
According to another aspect, a method for asymmetrically shielding a signal comprises determining a first probability of a signal being at a first value, determining a second probability of the signal being at a second value, positioning a first wire at a first distance from the signal, and positioning a second wire at a second distance from the signal, where the first distance is dependent on the first probability and the second distance is dependent on the second probability.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.